One current technological trend is to develop an integrated circuit having an operating speed (frequency) greater than that of its predecessors. Electronic noise can hinder the operation of the circuit. The noise interference is especially pronounced at the higher frequencies. To correct this problem, conventionally, the number of power lines and ground lines has been increased in proportion to the number of input/output (I/O) lines in an integrated circuit (IC) package. Following the conventional approach, as each successive VLSI is designed, the number of power lines and ground lines is greater than that of the previous design. It is predicted that the number of power lines and ground lines will eventually equal the number of I/O lines. As such, future IC packages will be physically larger and more structurally complex than their present counterparts.
A solution to this problem, as well as to many other integrated circuit problems, is to mount a capacitor chip on the IC package. Providing the IC package with a capacitive chip reduces the number of power lines and ground lines required. However, when a capacitor chip is added, the inductance of a power line/ground line loop is increased, possibly to five times the value of the inductance present when no capacitor chip is used. As a result, it is expected that five or more chip capacitors in parallel must be mounted onto the IC package to reduce that inductance. Since it is expected that the number of power line/ground line loops can only increase, given the current VLSI development trend, it is predicted that twenty or more capacitor chips would be required for an IC package given 100 power line/ground line loops. As with the conventional method of simply adding power line/ground line loops, adding chip capacitors complicates the IC package and reduces reliability and yield.
A solution to the foregoing problems is to provide a capacitor function within a multilayer wiring substrate. However, to provide the capacitor function in this manner, it has been necessary to use sheets or paste having the same composition as the substrate. It has also been necessary to laminate the conductors and the sheets or paste in multiple layers to obtain a predetermined capacitance.
U.S. Pat. No. 5,099,388 is directed to an alumina multilayer wiring substrate having a high dielectric, low inductance capacitor in the substrate on which a VLSI is to be mounted to effectively eliminate electrical noise(s) which may hinder the operation of the VLSI at high speed (frequency).
The present invention addresses a structure which further eliminates noise that may hinder the operation of the VLSI at high frequencies (speeds). It is possible to provide an alumina multilayer substrate in which a low inductance capacitor is embedded by placing a very thin ceramic sheet of high dielectric material in the vicinity of a position where the VLSI chip is to be mounted.
To obtain a large capacitance through the described multilayer lamination method, the sheet or paste layer must be made thinner or the number of laminations of the sheet or paste layer must be increased. In this process, however, there have been problems reducing the sheet or paste layer thickness below 10 .mu.m. Moreover, increasing the number of laminations and steps increases cost. Reducing the number of laminations reduces reliability, etc.
Accordingly, it would be advantageous to provide a wiring substrate with a high capacitance.
The primary object of the present invention is to provide a method of forming a wiring substrate with a buried electrode having a high capacitance.
Another objective of the present invention is to provide a method which consistently results in the formation of wiring substrate having high capacitance.
Yet another object of the present invention is to provide a method of forming a wiring substrate having a high capacitance which results in a low incidence of shorting between the counter electrodes in the capacitors.
These and other objects and advantages of the present invention will be more fully understood and appreciated with reference to the following description.